Microdevices, such as integrated microcircuits and microelectromechanical systems (MEMS), are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microdevices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microdevice fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected or the design is otherwise improved.
Several steps are common to most design flows for integrated microcircuits. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit can be described in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). As part of the creation of a logical design, a designer will also implement a place-and-route process to determine the placement of the various portions of the circuit, along with an initial routing of interconnections between those portions. The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices, such as transistors, resistors, and capacitors, which will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. Preliminary timing estimates for portions of the circuit may be made at this stage, using an assumed characteristic speed for each device. In addition, the relationships between the electronic devices are analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as “formal verification.”
Once the relationships between circuit devices have been established, the design can be again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements, which typically are polygons, define the shapes that will be created in various materials to manufacture the circuit. Typically, a designer will select groups of geometric elements representing circuit device components, e.g., contacts, gates, etc., and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Once the groups of geometric elements representing circuit device components have been placed, geometric elements representing connection lines then are then placed between these geometric elements according to the predetermined route. These lines will form the wiring used to interconnect the electronic devices.
Typically, a designer will perform a number of analyses on the resulting layout design data. For example, with integrated circuits, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships as described in the device design. The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements. Still further, the layout design may be modified to include the use of redundant geometric elements or the addition of corrective features to various geometric elements, to counteract limitations in the manufacturing process, etc. For example, the design flow process may include one or more resolution enhancement technique (RET) processes, that modify the layout design data to improve the usable resolution of the reticle or mask created from the design in a photolithographic manufacturing process.
After the layout design has been finalized, it is converted into a format that can be employed by a mask or reticle writing tool to create a mask or reticle for use in a photolithographic manufacturing process. The written masks or reticles then can be used in a photolithographic process to expose selected areas of a wafer to light or other radiation in order to produce the desired integrated microdevice structures on the wafer.
Returning to “functional verification,” this type of analysis begins with a circuit design coded at a register transfer level (RTL), which can be simulated by a design verification tool. A designer, for example, utilizing the design verification tool, can generate a test bench that can allow the design verification tool to analyze or verify the functionality of the simulated circuit design. There can be many different types of design verification tools, which can verify a variety of circuit design types, such as analog designs, digital designs, mix signal designs, combinations thereof, or the like, or specific architectural implementations, such as multiple clock-domain schemes, active power management schemes, or the like.
For active power management architectures, a design verification tool implementing power aware simulation, sometimes called a power aware design verification tool, can modeling an active power management scheme while simulating the circuit design. Since coding at the register transfer level does not include power domain-related circuitry, the circuit design can be annotated with a power intent, for example, expressed in a Unified Power Format (UPF) specification described by Institute of Electrical and Electronics Engineers (IEEE) Standard 1801. The power intent can include description of various power domain-related design intentions, such as power supply nets, power states, power controls, electrical protection schemes, memory retention schemes, or the like. Given the description of power intent, the power aware design verification tool can partition the circuit design into power domains, synthesize circuitry, such as isolation cells, level-shifting cells, retention cells, or the like, and integrate a power supply network into the circuit design to power each power domain. The augmented circuit design can then be simulated with control over power states for each domain, allowing for accurate modeling of active power management on design functionality.
The power aware design verification tool can perform various static checks, for example, during compilation of the circuit design and corresponding power intent, to identify architectural issues, such as missing or inadequate isolation or level-shifting cells in the power intent, prior to synthesis of any isolation or level-shifting cells from the power intent. For example, the power aware design verification tool can analyze the circuit design to determine where the circuit design may want to include isolation or level-shifting cells, such as at interconnections between different power domains, and then utilize power states of the different power domains, i.e., described in one or more power state tables of the power intent, to determine whether the power intent is missing or includes inadequate description of isolation or level-shifting cells.
Due to the complexity of many circuit designs, rather than have one monolithic power state table that describes every available power state in the circuit design, many power intent specifications include multiple power state tables that each include one or more power states for various combinations of power supplies available in the circuit design. When faced with an interconnection between different power domains to analyze, the power aware design verification tool can analyze the interconnection when the power states of the different power domains are described in one of the power state tables. Otherwise, the power aware design verification tool can indicate that the interconnection and any corresponding isolation or level-shifting cells were not analyzed for lack of an adequate power state table in the power intent specification.